Remarkable advances have been made in the increase of integration and speed of a nonvolatile semiconductor memory device such as a flash memory. Particularly, high-capacity flash memories are often used, instead of hard disks. Further, such nonvolatile semiconductor memory device is not only used by itself but also widely used as part of a system LSI by being embedded therein, such as a microcomputer with a built-in flash memory.
To achieve device miniaturization, Patent Document 1 discloses a split gate type nonvolatile semiconductor memory device having a FinFET structure. FIG. 52A is the same drawing shown in FIG. 25A of Patent Document 1, illustrating a cross section of a memory cell taken along a line parallel to a direction in which a current flows through the memory cell. FIGS. 52B and 52C are the same drawings shown in FIGS. 25B and 25C of Patent Document 1, respectively. FIGS. 52B and 52C illustrate cross sections of the memory cell taken along lines that are perpendicular to the above line and that go through a select gate 500 and a memory cell gate 550 of the memory cell, respectively. Further, FIGS. 52D and 52E are the same drawings shown in FIGS. 29 and 32 of Patent Document 1, respectively, illustrating plan views of other layout patterns. As shown in FIG. 52A, by forming the split gate type memory cell gate 550 adjacent to a side wall of the select gate 500 in a self-aligned manner, the select gate 500 and the memory gate 550 are formed close to each other in a small area. Further, as shown in FIGS. 52B and 52C, a channel region of a semiconductor substrate 100 is allowed to protrude into the select gate 500 and the memory gate 550, and not only the top surface but also the side walls of the protruded part of the semiconductor substrate 100 are used as a channel region to form a FinFET structure. In this way, an on-state current can be secured in a narrow width.
This memory cell is driven by applying positive voltages to the memory gate 550, the select gate 500, and a drain 310 and controlling the current flowing between the source 210 and the drain 310 based on the presence of electric charges in a charge storage layer 950. The protruded channel region shown in FIGS. 52B and 52C is formed by digging into a shallow trench isolation (STI) of the memory cell region and embedding the memory gate 550 and the select gate 500.
Further, as shown in the plan view of FIG. 52D, since the memory gate 550 is formed after the select gate 500 is formed, memory gate polysilicon may remain on side walls of a diffusion layer in the STI. Even in such case, by forming the STI in the form of an island and longitudinally installing the source 210 as a common source line, a memory gate polysilicon process residue 1555 formed on side walls of a diffusion layer in the STI does not form a short circuit of adjacent memory gates.
As shown in FIG. 52E, Patent Document 1 also discloses another example of the array in which the polysilicon process residue 1555 is actively used to short out adjacent memory gates in advance. In this case, shorted-out memory gates cannot be controlled individually.
Next, operations of the nonvolatile semiconductor memory device disclosed in Patent Document 1 will be described. For writing, positive voltages of (4.5 V and 5.5 V, for example) are applied to the source 210 and the memory gate 550, respectively. Further, a positive voltage lower than the voltage applied to the memory gate 550 is applied to the select gate 500, and the drain 310 is connected to ground. When these voltages are applied, some of the electrons flowing from the drain 310 to the source 210 are accelerated in the channel under the memory gate 550, and an ONO film under the memory gate 550 is implanted with some of the electrons, whereby writing is executed.
For erasing, a positive voltage (4.5 V, for example) is applied to the source 210, and a negative voltage (−3.0 V, for example) is applied to the memory gate 550. When these voltages are applied, electron-hole pairs are generated by interband tunneling in the source 210 under the memory gate 550, and some of the holes are accelerated by the electric field of the source 210. The ONO film is then implanted with the holes, whereby erasing is executed. The voltage applied to the select gate 500 for erasing may be 0 V or a negative voltage (0 V to approximately −3 V).
For reading, the source 210 is connected to ground, a positive voltage (2 V, for example) is applied to the memory gate 550 and the select gate 500, and a positive voltage (1 V, for example) is applied to the drain 310, to detect a current flowing between the drain 310 and the source 210. Information is read by using such characteristics that a smaller current flows when electrons are trapped in the ONO film (in a written state) and a larger current flows when holes are trapped or almost no electrical charges are trapped (in an erased state). During reading, electrons flow in a direction opposite to that during writing, and in this way, erroneous writing caused by disturbance is prevented.    Patent Document 1: Japanese Patent Kokai Publication No. JP-P2006-41354A